In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the tiny block of processed semiconducting material (i.e., an integrated circuit (IC) chip or die) is encased in a supporting case that prevents physical damage and corrosion. The case, known as a “package”, typically includes a package substrate that supports and provides electrical contacts between the packaged IC chips and an external circuit board. There are many electronic package types for both single and multiple die arrangements, and a few different methods for interconnecting the IC chips and package substrate. A case or cover is often secured or formed over the interconnected IC chips and package substrate for protection.
Wire bonding is the primary method of making interconnections between an IC chip and a package substrate in an electronic package. Wire bonding is performed by high-speed bonding machines that pushes a suitable metal (e.g., copper) though an outlet to form a first (ball or wedge) bond on a target contact pad of an IC chip, then forms a wire while moving to the outer periphery of the IC chip, then forms a second bond on an associated contact pad in a peripheral area of the package substrate. The resulting wire bond is very tolerance of production and thermal expansion mismatch variances. That is, manufacturing imperfections in the IC chips are easily tolerated by forming large contact pads that are reliably contacted by the wire bonding machine. Also, the long wire flexes to tolerate thermal expansion mismatches between the die and package substrate, thereby avoiding unwanted disconnections that can cause system failures.
Although wire bonds provide design tolerances to production and thermal mismatches, there are multiple problems with the wire bond interconnect approach. First, the relatively long wire bonds create large parasitics, such as high inductance, which reduces the bandwidth of the packaged system. Second, the footprint of package utilizing wire bonding is relatively large because the package substrate must be significantly larger than the IC chips to provide for connection to the lower ends of the wire bonds, which are disposed around the perimeter of the IC chips. Also, the height of the resulting wire bond package is relatively tall because each wire bond requires an arch or loop for structural integrity reasons that extends significantly above the upper surface of the packaged IC chips. Finally, the density of wire bond interconnects is low because the wire bonds are long, and because it is very difficult to create a large number of wire-bond connections in a small area without danger of the wires making undesirable contact with each other.
Stacked-die Multi-Chip Module (MCM) packaging is an electronic package type in which two or more die mounted on top of each other in a single package to significantly increase the amount of silicon chip area for a given package footprint, conserving precious real estate on a host system's printed circuit board, and simplifying the board assembly process. Aside from space savings, die stacking also results in better electrical performance of the device, since the shorter inter-package routing connections between the two or more chips/circuits results in faster signal propagation and reduction in noise and cross-talk. Early stacked-die MCM packages included two memory chips, such as Flash and SRAM devices, but more recent die-stacking arrangement now involve up to six or more chips of varying function or technology, e.g., logic, analog, mixed-signal, etc.
Stacked die MCM arrangements include pyramid-type and equal-size die stacking arrangements. In pyramid-type stacking arrangements, different sized die are stacked with the smaller die concentrically disposed on top of larger die, providing an arrangement that is conductive to wire bond interconnects because the outer perimeter of each die is exposed for access by the wire bond forming machine. Equal-size die stacking allows for larger total chip area than pyramid-type stacking arrangements, but restricts wire bond connections to the uppermost die in the stack.
Solder-based flip-chip connections, also known as controlled collapse chip connection or its acronym, C4, represent another method for interconnecting equal-size stacked IC chips in an MCM package by way of solder bumps that have been deposited onto the chip contact (input/output) pads. In order to mount the chips to external circuitry (i.e., a package substrate or a neighboring IC chip), it is flipped over so that its top side faces down, and aligned so that the deposited solder bumps align with matching pads on the neighboring IC chip or package substrate, and then the solder is flowed to complete the interconnect. In comparison to wire bond interconnects, the solder-based flip-chip interconnect approach facilitates higher system bandwidths, a smaller package footprint (i.e., because all of the connections are disposed between the IC chip stack and the package substrate), and a lower package height (due to the elimination of the wire bond loops).
Although solder-type flip-chip technology provides several advantages over wire bond interconnections, the solder-based flip-chip approach requires that the stacked IC chips be fabricated to include expensive through-chip electrical vias in order to create access to the backside of each chip. Also, flip-chip technology provides very little tolerance for production and thermal expansion mismatch variances. That is, manufacturing imperfections in the IC chips can result in failure to complete one or more required connections, or thermal expansion mismatches between the die and package substrate materials can cause solder cracks and separation that creates system failures.
What is needed is a packaging technology that provides both the production and thermal tolerances of wire bond interconnects, and the higher density and bandwidth associated with solder-based flip-chip interconnects.